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SNUG Israel 2005 Proceedings
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User Papers
A1: Functional Verification Techniques
Module and System Level Verification Environment for System On Chip Devices
Author(s): Yehezkiel Tzadik, Eli David [Intrinsix Israel Ltd]
PaperPresentation

Off-line Debugging and Testing of On-Line Checkers
Author(s): Mark Mostow [IBM]
PaperPresentation

PCI Bridge Verification with Synopsys VIP
Author(s): Ohad Tzadik [Adimos Wireless Multimedia]
PaperPresentation
A2: Low Power Techniques
How to Save Power in High-Frequency Design
Author(s): Ina Shtarkberg, Oleg Milter [Intel Corporation]
PaperPresentation

Integration of Power Analysis and Optimization in the ASIC Design Flow
Author(s): Efi Dalumi [Conexant Systems Inc]
PaperPresentation

PrimeTime Tool for Noise Aware Multi VT Optimization
Author(s): Asaf Shoham, Eddie Reizin, Gil Moran [Freescale Semiconductor Israel]
PaperPresentation
A3: Physical Design
An Automated Datapath Placement and Routing Flow Using Astro
Author(s): Baruch Gudesblat, Andreas Olofsson [Analog Devices Israel]
PaperPresentation

Embedding PrimeTime In All Implementation Flow Steps
Author(s): Roy Mimran [Tower Semiconductor Ltd]
PaperPresentation

Fixing Hold (min_delay) Violations with Physical Compiler after Back-Annotation in Min/Max Mode
Author(s): Oren Porat [Freescale Semiconductor Israel]
PaperPresentation
B1: Transistor Level and Process Analysis
Design Guidelines for Successful Design and Timing Analysis of Semi-Custom Datapaths using Pathmill (1st Place - Best Paper)
Author(s): Andreas Olofsson, Henri Meirov [Analog Devices Israel]
PaperPresentation

From DRM to Design - Creation of Parasitics Extraction Process Description
Author(s): Ezra Cohen-Yashar [Tower Semiconductor LTD]
PaperPresentation
B2: Analog Design Verification Techniques
Post Layout Circuit Verification of Memory Design Using Nanosim
Author(s): Natan Yahav [Freescale Semiconductor Israel]
PaperPresentation

Verification Methodology for Mixed Analog/Digital Chips
Author(s): Nimrod Blatt [National Semiconductor]
PaperPresentation
B3: Logic Design and Test
SystemVerilog's priority & unique - A Solution to Verilog's "full_case" & "parallel_case" Evil Twins!
Author(s): Clifford E. Cummings [Sunburst Design Inc]
PaperPresentation

Test Pattern Generation for Sub-Micron Chips
Author(s): Itai Yarom [Intel Corporation]
PaperPresentation
Tutorials
TA1
Power Management Techniques for Design Closure
Author(s):
Tutorial
TA2
Power Integrity Analysis to Ensure Design Reliability
Author(s):
Tutorial
TB
Synopsys 2004.06 Galaxy Signal Integrity Flow Updates and Best Practices: Sign-off with PrimeTime SI
Author(s):
Tutorial
TC
Design Compiler XG, Physical Compiler XG, Astro Recommended Methodology
Author(s):
Tutorial
TE1
Synopsys' Complete Verification Solution for Variety of Full Custom Analog Mixed-Signal Designs
Author(s):
Tutorial
TE2
CONTINUED (TE1): Synopsys' Complete Verification Solution for Variety of Full Custom Analog Mixed-Signal Designs
Author(s):
Tutorial


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