| User Papers |
| A1 - Implementation / DC Graphical |
Chip Size Reduction Using Ultra Compile - A Case Study
Author(s): Bernhard M Riess [Infineon Technologies AG] |
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Congestion Correlation Between DC Topographical and IC Compiler
Author(s): Sylvie Pierunek [STMicroelectronics], Gladys Renard [Synopsys] |
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DC Graphical: The Promise and the Reality
Author(s): Phil Watson [ARM, Ltd.], Tom Fairborn [Synopsys] |
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| A2 - FastSPICE and Mixed-Signal Simulation |
Evaluation of Four Popular Fastmos Tools for Simulating DRAM Circuits (3rd Place - Best Paper)
Author(s): Horst Fischer, Guoxing Zhang, Holger Günther [Qimonda AG] |
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HSIMplus Based Mixed-Signal Design and Verification
Author(s): Pierluigi Daglio, Salvatore Santapà, Alessandro Valerio [STMicroelectronics] |
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XA SPICE Accelerator Solution for Analog IP Verification at ChipIdea/MIPS
Author(s): Asdrubal Mendes [MIPS], Patrice Loth [Synopsys] |
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| A3 - System Design and Verification with C and SystemVerilog |
Creating Encrypted Simulation Models with System Studio
Author(s): Mika Vaittinen [Nokia] |
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Seamless Refinement from Transaction Level to RTL Using SystemVerilog Interfaces (2nd Place - Best Paper)
Author(s): Jonathan Bromley [Doulos Ltd.] |
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Unified Verification and Prototyping Using SystemVerilog DPI and VhPI
Author(s): Michael Rumsey [CSR], Yassine Eben Aimine [Synopsys, Inc.] |
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| B1 - Low Power Implementation and Power Estimation |
Complex Low Power Multi-VDD Implementation Using SNPS Point Tools
Author(s): Tariq El Motassadeq, Nijam Mohamed, Syed Thameem, Dhaval Bhatia, Ramy Gamal, Vijay Sarathi [Dubai Circuit Design] |
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Gate-Level Power-Estimation in Primetime-PX with RTL Simulation
Author(s): Philip Cuney [STMicroelectronics] |
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Low-Power Implementation Flow using UPF
Author(s): Laurent Besson [STMicroelectronics] |
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| B2 - AMS - HSPICE |
Models for High Speed Serial Links – HSPICE and AMI
Author(s): Katja Koller [Nokia Siemens Networks] |
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Package Model Evaluation with HSPICE
Author(s): Manfred Maurer [Siemens AG] |
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| B3 - VMM and Hardware Verification |
Leveraging VMM for the SystemVerilog-Based Verification of Cache-Based SoC Architectures
Author(s): Jerome Bombal, Fabien Camus [Texas Instruments France] |
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Lies, Damn Lies and Hardware Verification
Author(s): Michael Bartley [Test and Verification Solutions] |
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Super vmm_data! Automating vmm_data Methods in Data Structures
Author(s): Kevin Hyland, Vishal Patel [CréVinn Teoranta] |
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| C1 - Noise Reduction and Sign Off Checks |
Cruise Control Flow for Sign Off Density Metal Fill and DRC “that is making sense”
Author(s): Sven Seydler [Intel GmbH], David DeMarcos [Synopsys, Inc.] |
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Cruise Control Flow for Sign Off Density Metal Fill and DRC “that is making sense”
Author(s): Sven Seydler [Intel GmbH], David DeMarcos [Synopsys, Inc.] |
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Cruise Control Flow for Sign Off Density Metal Fill and DRC that is making sense”
Author(s): Sven Seydler [Intel GmbH], David DeMarcos [Synopsys, Inc.] |
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Power Rail Noise Minimization for EMC-Aware Design
Author(s): Patrice Joubert Doriol, Cristiano Forzan, Davide Villa, Davide Pandini, Renato Castellan, Daniele Cervini, Mario Rotigni, Giovanni Graziosi [STMicroelectronics], Giuseppe Contarino, Egidio Marzorati [Synopsys] |
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Using PrimeTime's Advanced On-Chip-Variation Modeling (AOCVM) to Reduce Pessimism of Global Derates
Author(s): Thomas Haase [NEC Electronics GmbH] |
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| D1 - Backend Design Methodology and Examples |
Adopting PILOT Flow for 65nm Multi-Million Instance Hierarchical Design
Author(s): Syed Thameem, Nijam Mohamed, Khalid Laarif, Vikram Virdi, Anas Fareed [Dubai Circuit Design] |
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Automatic I/O Placement and Connectivity with Astro and Spreadsheet
Author(s): Michael Lortz, Martin Embacher [National Semiconductor] |
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Clock Domain Aware Spare Cells Insertion and Spreading
Author(s): Elvio Romanucci, Deepti Miyan [STMicroelectronics CPG], Aurelio Monti [Synopsys] |
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| D2 - ATPG Challenges and Solutions |
Full Hierarchical Flow for Custom On-Chip Controller and Scan Compression Insertion for At-Speed Testing
Author(s): Franco Cesari, Paolo Giovacchini - STMicroelectronics; Salvatore Talluto, Alfredo Conte - Synopsys, Inc. |
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Small Delay Defect Experiments on a Complex SoC
Author(s): Fahd Jaadane Rachdi, Khalid Zouita [ST-NXP Wireless], Philippe Rossant [Synopsys] |
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Transition Fault Test Pattern Generation Optimization using On-Chip PLL and Implication on Compression Techniques (Technical Committee Award Honorable Mention)
Author(s): Frederic Hiebel [Texas Instruments Inc.] |
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| D3 - SystemVerilog and SVA |
A Migration from Vera to SystemVerilog in a Stepped Approach
Author(s): Joachim Geishauser, Wolfgang Mair, Daniel Hoheisel [Freescale GmbH] |
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Combine Protocol Checking in SVA with the Object Oriented Testbench Structure!
Author(s): Nils Bossemeyer, Frank Donner, Joachim Fader, Michael Pallas, Michael Rohleder [Freescale Semiconductor GmbH] |
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Progressive Migration from 'e' to SystemVerilog: A Case Study
Author(s): Christopher Brown, Dave Wiltshire, Neil Bulman [Texas Instruments Ltd], Yassine Eben Aimine [Synopsys, Inc.] |
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| E1 - ICC Design Experience |
Hierarchical Implementation of Cortex-A9 MPCore Multicore Processor with Galaxy Platform
Author(s): Saran Kumar Seethapathi, Arvind Kumar Sharma, Rahoul Varma [ARM Embedded Technologies Pvt Ltd.], Subrata Sen [Synopsys] |
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Using ICC's minChip to Explore Digital Block Sizing and Row to Core Ratio for Optimal Fit into Mixed Signal Designs
Author(s): Ralf Eckhard Stephan [Robert Bosch GmbH], Jens Peters [Synopsys] |
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| E2 - DFT Implementation for Complex SoCs |
Advanced DFT Implementation Using SNPS DW Components and Galaxy Test (Technical Committee Award Honorable Mention)
Author(s): Manu Baby, Vijay Sarathi [Dubai Circuit Design] |
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Design For Test Insertion on a Very Complex VLSI Using Synopsys Galaxy Flow (Technical Committee Award)
Author(s): Cyrille Thomas [Bull SAS] |
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Implementation of At-Speed Test using an On-Chip Clock Controller on an Analog Devices Audio Processor
Author(s): Shane Gallagher, Gabriel Gomez, Brian Coffey [Analog Devices, Inc.] |
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| E3 - VMM RAL |
Automation Around VMM-RAL
Author(s): Richard Willems, Johannes Bauerle [Thomson TSC] |
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Automation Around VMM-RAL
Author(s): Richard Willems, Johannes Bauerle [Thomson TSC] |
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| Saber Mixed Technology & Wiring Harness Design |
Active Filters in Marine Applications
Author(s): Richard Baumgartner, Simon Jones [CONVERTEAM SAS] |
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Automating Saber with TCL/TK and AIM: Electrical Load Extrapolation and Schematic Generation (1st Place - Best Paper)
Author(s): Jörg Christoffers [EADS Innovation Works] |
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Behavioral Model of a Headlamp Leveling System
Author(s): Ewald Hessel [Hella KGaA Hueck & Co.] |
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Modeling and Simulation of Multi Degree-of-Freedom Micro-Machined Accelerometer with Sigma-Delta Modulator (Best First-Time Presenter)
Author(s): Christopher J. Welham, Gunar Lorenz, Stephane Rouvillois [Coventor Sarl], Michael Kraft [Southhampton University], David King, David Combes, Mark McNie [QinetiQ] |
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Modeling of Mechatronical Devices with Saber
Author(s): Sergey Petkun [Brose Fahrzeugteile GmbH] |
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Release of Schematics and Bundles from Saber in an Already In-Place Release System
Author(s): Ronny Thijs, Marco Putnams [DAFtrucks] |
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Using Saber Harness / Bundle in a Global Product Development Environment
Author(s): Julien Bidault [Volvo IT] |