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SNUG Boston 2001 Proceedings
2009
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Tutorials
MA1
Timing Closure Methodology using Physical Compiler Kwam Ewusie - Synopsys, Inc
Author(s):
Tutorial
MA2
What's New in VCS? John Girard, Quinn Canfield, Bill Dufresne - Synopsys, Inc.
Author(s):
Tutorial
MA4
Programmable System-on-a-Chip Synthesis Using FPGA Compiler II Alex Choi - Synopsys, Inc.
Author(s):
Tutorial
WA1
Static Crosstalk Analysis with PrimeTime -SI Richard Holt - Synopsys, Inc.
Author(s):
Tutorial
WA2
An Introduction to Using VERA for Design Verification Chris Spear - Synopsys, Inc.
Author(s):
Tutorial
WA3
Physical Synthesis Hierarchical Design Flow Frank De Meersman, Suresh Nair - Synopsys, Inc.
Author(s):
Tutorial
WB2
DFTC and TetraMAX 2001.08 Update Lionel Corbet - Synopsys, Inc.
Author(s):
Tutorial
WB3
Modeling Systems with SystemC 2.0 Kurt Schwartz - Willamette HDL, Inc.
Author(s):
Tutorial
WB4
Enabling Low Power Design and Power Verification with Power Compiler and PrimePower Mike Borghese - Synopsys, Inc.
Author(s):
Tutorial
Speech
Guest Speaker
The Verification of SoC Designs with VERA
Author(s):
Faisal Haque [Cisco]
Paper
Keynote Address
Survive and Thrive
Author(s):
Aart de Geus, Chairman and CEO [Synopsys, Inc.]
Paper
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