Get the Most from Your HSPICE Simulation
Unleash the power of HSPICE simulations with useful tips and tricks to reduce simulation time without compromising HSPICE’s gold-standard accuracy.
Szekit Chan, HSPICE Staff Corporate Applications Engineer, Synopsys
Nov 30, 2011 |
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Understand and Avoid Electromigration (EM) & IR-drop Effects in Custom IP Blocks
Learn how process technology & changing design styles increase the impact of EM & IR-drop effects on the performance/reliability of AMS, memory & custom digital IP blocks at 28nm and below.
Bradley Geden, Solution Architect, Synopsys
Oct 26, 2011 |
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Advanced Regression and Analysis for Mixed-Signal Verification Using CustomExplorer Ultra
Learn how CustomExplorer Ultra enables high verification productivity for complex SoCs using advanced strategies that surpass traditional verification approaches.
Duncan McDonald, Product Marketing Manager, Synopsys; Dwayne Holst, Corporate Applications Engineer, Synopsys
May 11, 2011 |
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Accurate Jitter and Noise Analysis Using HSPICE Transient Noise Techniques
Learn about new time-domain noise analysis approaches available in HSPICE, and how transient noise analysis can verify critical timing and noise performance characteristics.
Scott Wedge, Sr. Staff Engineer, Synopsys
May 04, 2011 |
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CustomSim and VCS Extend Digital Verification Techniques to Mixed-Signal Designs
Use CustomSim and VCS to create reusable mixed-signal verification environments that enable analog assertions, analog verification planning, analog stimulus and analog self-checkers to find bugs related to analog and digital interfaces sooner.
Bradley Geden, CustomSim Product Marketing Manager, Synopsys; Fabian Delguste, Principle Corporate Application Engineer, Synopsys
Jan 26, 2011 |
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Advances in Circuit Analysis with the Custom Designer Simulation and Analysis Environment
Learn how to efficiently use Custom Designer's SAE in conjunction with HSPICE and Custom WaveView to analyze a design across process and parameter variations.
Kristin Beggs, R&D Engineer, Synopsys
Oct 27, 2010 |
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Accelerate Analog Simulation with HSPICE Precision Parallel Technology
Learn how HSPICE Precision Parallel technology accelerates verification of analog/mixed-signal circuits up to 7X on 8 cores while maintaining gold-standard accuracy.
Hany Elhak, Product Marketing Manager, Synopsys; Fredrik Ivarsson, Corporate Applications Engineer, Synopsys
Oct 20, 2010 |
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Multi-Gigabit Signal Integrity Analysis with HSPICE
Learn about HSPICE capabilities for modeling high-frequency channel components, and high-performance simulation and analysis features for characterizing multi-gigabit links.
Scott Wedge, Ph.D, Sr. Staff Engineer, Synopsys
Aug 18, 2010 |
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Find Electrical Violations Before Tapeout with CustomSim Circuit Check
Learn how customers are using CustomSim Circuit Check to analyze designs with hundreds of millions of transistors to catch electrical violations before tapeout.
Bradley Geden, Product Marketing Manager, Synopsys
Jul 21, 2010 |
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Verify Digitally-Assisted Analog Circuits with CustomSim Fast Transient Analysis
Learn how the CustomSim high-capacity, fast transient analysis solution can help you increase design confidence and reduce project development time.
Bradley Geden, Product Marketing Manager, Synopsys; Tom Hsieh, AMS CAE, Synopsys
Mar 25, 2010 |
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CustomSim for Memory Timing & Power Analysis
This webinar highlights memory verification methodologies and how choosing the right methodology enables memory designers to produce the highest-accuracy timing and power measurements in the shortest turnaround time.
Bradley Geden, Product Marketing Manager, Synopsys
Dec 15, 2009 |
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Extraction Techniques to Accelerate High-Capacity Simulation
StarRC can enable up to 10x speed-up in simulation runtime while preserving golden accuracy. In this webinar our experts explain innovative techniques to boost simulation performance and capacity for your custom digital, memory or AMS designs.
Synopsys
Sep 22, 2009 |
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HSPICE StatEye – ISI Predictions Made Easy
Are your high-speed serial link simulations taking too long? Want to speed up your eye diagram generation and ISI predictions by 100X? If so, learn how to speed up high-speed serial link analyses and get the most out of the statistical eye diagram capability in HSPICE.
Christopher Labrecque, Marketing Manager, Synopsys
Apr 29, 2009 |
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Increase Design Confidence with CustomSim
Learn how CustomSim addresses verification challenges for a diverse array of functional blocks, including custom digital, analog and memory designs. Learn how to take advantage of multi-threading capabilities to achieve an additional 4x performance improvement.
Synopsys
Apr 28, 2009 |
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Robust SI Analysis of a DDR2 Interface with HSPICE
For years designers around the world have trusted HSPICE for their signal integrity simulation needs
Dr. Scott Wedge, Senior Staff Engineer, Synopsys; Ted Mido, Senior Staff Engineer, Synopsys
Feb 13, 2007 |
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Predicting PLL Phase Noise & Jitter with HSPICE RF
Due to today’s ever increasing data rates, phase noise and jitter specifications are now critical aspects of modern phase-locked loop design.
Dr. Scott Wedge, Senior Staff Engineer, Synopsys
Jan 03, 2007 |
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