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A View from the Top: A System-Level Blog
This blog will deal not only with the shift towards adoption of virtual platforms but with ESL technologies in general.
F. Schirrmeister, J. Stahl, M. Serughetti, T. Schutter, P. Sheridan
Analog Insights Blog: Analog/Mixed-Signal Design and Verification
Observations and views from 3 of Synopsys’ top AMS/custom design technologists.
Fred Sendig, Kishore Singhal, Bob Lefferts
Verification Martial Arts
In SystemVerilog, unlike C, you don’t have to explictly free dynamically allocated class instances.
Janick Bergeron
The Standards Game
Hello, everyone interested in EDA interoperability and fans of The Standards Game. I’d like to invite you to join me at the 21st Synopsys EDA Interoperability Forum, sponsored by Sun Microsystems.
Karen Bartleson
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NEWS
Synopsys HSPICE Simulator Delivers 6X Faster Throughput for Intrinsity's 45-nmTechnology
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HSPICE - The Gold Standard for Accurate Circuit Simulation
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Synopsys HSPICE Simulator Delivers 6X Faster Throughput for Intrinsity's....
Synopsys Discovery AMS Enables Analog Bits to Achieve 45nm SERDES Verification
Synopsys and TSMC Collaborate on Advanced HSPICE Modeling Technology for 40-nm....
Synopsys Launches HSPICE Integrator Program With 25 Founding Members
Synopsys HSPICE Simulator Accelerates ARM's 45-Nanometer Physical IP Development
Synopsys HSPICE Simulator and SISoft Deliver Signal Integrity Analysis Solution
Agilent Technologies Announces HVMOS Package for Synopsys' HSPICE
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Articles
Migrating Complex Networking ASIC Verification Environment
Synopsys tries to organize its efforts in EDA multiprocessing
Verify SoCs Faster And More Predictably With SystemVerilog And Constrained-Random Stimuli
VMM application packages- the next level of productivity
IC verification key: ‘Do it step by step, don’t cut corners’
Nightmares in Functional Verification
Future Verification Appears Uncertain
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Blogs
A View from the Top: A System-Level Blog
Analog Insights Blog: Analog/Mixed-Signal Design and Verification
Verification Martial Arts
The Standards Game
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Webinars
Get the Most from Your HSPICE Simulation
Avoid EM & IR-drop Effects in Custom IP Blocks
Regression and Analysis for Mixed-Signal Verification
Jitter Analysis Using HSPICE Transient Noise Techniques
Mixed-Signal Design Verification Techniques
Advances in Circuit Analysis with Custom Designer SAE
Accelerate Analog Simulation with HSPICE
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NanoSim
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