| Yield Metrology Looking at Systematic Failure |
Sagar Kekare of Synopsys discusses his paper on rapid root cause analysis and process change validation using design-centric volume diagnostics in a video interview with Debra Vogler of Solid State Technology.
Jul 14, 2010 |
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| EDN: Design-centric yield management |
In the race to the market, IC vendors have few avenues remaining to claim the first-to-market advantage.
Mar 12, 2009 |
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| EDN: Synopsys tries to organize its efforts in EDA multiprocessing |
It’s hard to imagine a set of applications that need computing resources more than the chain of EDA tools for a 65 nm chip design. (OK, searching for extraterrestrials, maybe, but the economics are a bit different there.)
Mar 10, 2008 |
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| Semiconductor International: Nikon and Synopsys deliver on Advanced OPC promise |
The latest release of Synopsys's Proteus optical proximity correction (OPC) software now incorporates proprietary data from Nikon's lithography exposure tools.
Oct 13, 2007 |
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| Chip Design: EDA Is Stepping Up to Meet New DFM Demands |
"Smaller, faster, and cheaper” has been the mantra of the semiconductor industry for over 40 years. But the latest 45- and 32-nm technology nodes have many in the semiconductor industry crying “uncle.”
Oct 13, 2007 |
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 A New Approach to Higher Yielding Silicon |
The production of leading edge semiconductors relies on a delicate balance between design and manufacturing.
Apr 01, 2007 |
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| Model-Based Metal Fill Optimizes Planarization and Increases Yield |
Copper interconnect was introduced to the mainstream at 130nm because of its significant advantages compared to aluminum, such as reduction in resistivity and power consumption and resistance to electromigration.
Mar 22, 2007 |
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| DFM In Action |
In the post-physical verification space called 'Mask Synthesis' a key component of design-for-manufacturing (DFM), double-exposure based, dark-field, alternating PSM (Alt-PSM) is being increasingly applied at the 90nm node.
Dec 01, 2005 |
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