As 32/28nm design challenges increase, we want to share input from others in the industry along with solutions available in IC Compiler and the Synopsys Galaxy platform. Join us for one or more of the following webinars. Check back to register for future events.
January 26
32/28nm challenges - The EDA Vendor and Foundry Perspective
This webinar is the first in a series highlighting 32/28nm design challenges and the solutions available in IC Compiler and the Synopsys Galaxy platform to address these challenges. It will be a joint presentation featuring speakers from Synopsys and TSMC to provide you with the EDA vendor and foundry viewpoints.
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April 8
Addressing 32/28nm Design Challenges
In this webinar Synopsys will share their design solution that addresses 32/28nm challenges. Advanced technologies in core areas that consider both the effects of nanometer processes as well as the exploding design complexity will be showcased. Learn how to get the best QoR, faster design closure and reduce design cost.
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June 9
Fastest Time to Tapeout with IC Validator
Design complexities at 32nm and below mandate a new approach to Physical Verification predicated upon a high-performance, hybrid signoff engine. IC Validator is a foundry-qualified signoff DRC/LVS tool which has been successfully deployed at leading IDMs and Fabless customers and was architected to eliminate late-stage surprises through In-Design Physical Verification with IC Compiler. This webinar highlights several high productivity IC Validator flows and features.
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July 28
Realizing Today’s 32nm and Beyond Large Capacity Designs
Synopsys Design Planning R&D will highlight the latest hierarchical design exploration and planning technology available in IC Compiler for handling today’s large 32/28nm designs.
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August 11
Manufacturing-Aware Routing at 32/28nm
With the advent of each new technology node the complexity of doing design has increased and the need to consider yield as one of the objectives during design is now considered a necessity at the 32/28nm node. In this webinar we will discuss how IC Compiler’s Zroute Technology is built to consider manufacturability as one of the objectives of routing along with the techniques to address manufacturing during routing.
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September 14
Fast Gold-Standard Extraction at 28nm with StarRC
Increasing design complexity and the impact of new parasitic effects make accuracy and productivity for IC design and signoff analysis even more challenging beyond the 28nm process node. In this webinar, Synopsys experts will discuss how StarRC addresses these advanced challenges at 28nm through silicon-accurate modeling and high-performance extraction, enabling SoC designers to achieve signoff with increased confidence.