Overview of challenges of verifying a coherent design. Shows how the features and architecture of Synopsys’ new Discovery VIP helps overcome these challenges to simplify verification of ACE design.
Abhijeet Khopkar, R&D Manager, Synopsys; Neill Mullinger, Group Marketing Manager, Synopsys
May 08, 2012

Learn about VCS’ most recent technology advancements and new features enabling productivity in the following key areas: performance and capacity, verification planning, coverage and debug.
Michael Sanie, Director of Product Marketing, Synopsys; Shekhar Mahatme, Senior Staff Application Engineer (Verification Methodology), Synopsys
Sep 21, 2011

Learn about the latest improvements in verification performance and productivity including the new Synopsys features offered in support of standards-based SystemVerilog verification methodologies.
Adiel Khan, Senior Staff Engineer, Synopsys; Kiran Maiya, Corporate Application Engineer, Synopsys; Michael Sanie, Director of Product Marketing, Synopsys
Jul 28, 2011

Learn how CustomExplorer Ultra enables high verification productivity for complex SoCs using advanced strategies that surpass traditional verification approaches.
Duncan McDonald, Product Marketing Manager, Synopsys; Dwayne Holst, Corporate Applications Engineer, Synopsys
May 11, 2011

This Webinar will highlight recent advances in Synopsys verification IP technology that build on a pure SystemVerilog implementation.
Bernie Delay, Director R&D, Verification Goup, Synopsys; Steve McMaster, R&D Engineer, Verifiction Group, Synopsys; Zongyao Wen, R&D Manager, Verification Group, Synopsys
Apr 21, 2011

ESP-CV performs functional equivalence checks between a Verilog design and its transistor level implementation. The designs may be described as Verilog behavioral models, RTL, or gates, and a SPICE netlist. The new redundancy verification features in ESP-CV provide the ability to quickly and efficiently verify memory designs implemented with row and column redundancy.
Dave Hedges , CAE, Implementation Group, Synopsys; Clay McDonald, R&D Manager, Implementation Group, Synopsys
Jan 19, 2011

As the challenge of verification continues to grow, engineers are increasingly turning to verification planning, advanced coverage techniques and unique coverage technologies to optimize the tracking of verification progress and significantly improve the quality of their designs. In this webinar, you will learn about the latest advances in verification planning, coverage and coverage methodology. In addition, you will also discover some of the unique advantages of using VCS, including VCS’ Echo testbench coverage convergence technology.
Albert Chiang, Product Marketing Manager, Synopsys; Paul Graykowski Applications Engineer, Synopsys; Jean Fong Applications Consultant, Synopsys; Vernon Lee, Principle Engineer, Synopsys; and Rahul Dani, R&D Engineer, Synopsys
Sep 08, 2010

Successful, cost-effective verificaiton of a design requires quick and early bug detection. In this webinar, you will learn how Synopsys' Magellan hybrid technology speeds up bug hunting and provides unique value to design and verification teams.
Krishna Balachandran, Director of Marketing Synopsys; Mandar Munishwar, Corporate Applications Engineer, Synopsys; Xiaolin Chen, Corporate Applications Engineer, Synopsys; Dan Benua, Principal Engineer, Synopsys
May 04, 2010

Learn how MVRC and Formality tools complement each other to statically verify your design from RTL to transistors.
Krishna Balachandran, Director of Product Marketing, Synopsys; Prapanna Tiwari, Staff CAE, Synopsys; Bob Hatt, Staff CAE, Synopsys
Apr 28, 2010

In this webinar, you will learn about the basics of transaction-level modeling, why it is needed, how it integrates with an RTL design and how the Synopsys VCS functional verification solution supports both transaction-level and pin-level debug in its Discovery Visualization Environment (DVE).
Albert Chiang, Product Marketing Manager, Synopsys; Yasser Khan, Sr. Corporate Applications Engineer, Synopsys; Dr. Bassam Tabbara, Senior Staff R&D Engineer, Synopsys; Brett Kobernat, Applications Consultant, Synopsys
Jan 27, 2010

Learn all about constraints and how their proper specification and use will help you quickly achieve your verification goals. Synopsys’ Magellan hybrid formal tool helps detect and debug over-constraining of your formal setup, thereby increasing your confidence in your formal verification results.
Krishna Balachandran, Director of Marketing, Synopsys; Mandar Munishwar, Corporate Applications Engineer, Synopsys; Xiaolin Chen, Corporate Applications Engineer, Synopsys; and Dan Benua, Principal Engineer, Synopsys
Nov 11, 2009

Learn how VCS multicore technology allows users to reduce verification time for long-running tests by leveraging their multicore computing infrastructure. We cover VCS multicore technology’s two flexible use models: application-level parallelism (ALP) and design-level parallelism (DLP).
Chiang, Product Marketing Manager, Synopsys; Usha Gaira, Corporate Applications Engineer, Synopsys; Amitabh Chand, Corporate Applications Engineering Manager, Synopsys; and Jatinder Goraya, Research and Development Engineer, Synopsys
Oct 27, 2009

VMM base classes, VMM Applications and VMM-LP are deployed worldwide to address the toughest verification challenges. In this webinar, our experts cover new enhancements like TLM 2.0 support, improved block-to-top reuse heirarchical phasing and additional ease-of-use deployment features.
Albert Chiang, Product Marketing Manager, Synopsys; Yassine Eben Amine, Applications Consultant, Synopsys; and Kiran Maiya, Senior Corporate Applications Engineer, Synopsys
Oct 13, 2009

Learn how Synopsys' Magellan seamlessly integrates formal verification with simulation to achieve complete verification of today's complex designs.
Krishna Balachandran, Director of Verifiation Marketing, Synopsys; Xiaolin Chen, Corporate Applications Engineer, Synopsys; Mandar Munishwar Corporate Applications Engineer, Synopsys; Dan Benua, Principal Engineer, Synopsys
Aug 25, 2009

An understanding of the impact on verification from the deployment of low power design techniques is key to successful verification. Learn why verification has changed for low power designs and how Synopsys' VCS with MVSIM and MVRC comprehensively and accurately meet these challenges.
Krishna Balachandran, Director of Low Power Verification Marketing, Synopsys; Prapanna Tiwari, Corporate Applications Engineering Manager, Synopsys
Aug 11, 2009

In this webinar, we focus on the bug types that are new to low power design and introduce a structured and reusable methodology highlighting VMM extensions to base classes for low power that can be quickly used to replicate an efficient verification environment for low power designs.
Krishna Balachandran, Director of Low Power Verification Marketing, Synopsys; Srikanth Jadcherla, Group Director of R&D, Synopsys; Janick Bergeron, Synopsys Fellow, Synopsys
Aug 11, 2009

The Discovery Visualization Environment (DVE) offers unified debug and analysis of Verilog, VHDL, C/C++/SystemC, SystemVerilog Assertion/Design/Testbench and analog waveforms. Learn about DVE features such as coverage, planning, and interactive debug of a VMM environment with SystemC.
Albert Chiang, Technical Marketing Manager, Synopsys; Yasser Khan, Applications Engineer, Synopsys; Don Walters, R&D Manager, Synopsys;
Apr 30, 2009

Learn how VCS constraint solver technology can increase design quality while accelerating verification and minimizing cost. In addition, the speakers address debugging and profiling of constraints and discuss a few "tips and tricks" that help simplify constraint writing.
Synopsys
Jan 29, 2009