Training

Courses
Training Options

Verification
Functional Verification Courses

	SystemVerilog Assertions	This class teaches the key features of the SystemVerilog Asssertion language and its use in VCS, including how to create reusable, scalable assertions and assess the effectiveness of your testbench. Schedule

	SystemVerilog Testbench	In this intensive, three-day course, you will learn the key features and benefits of the SystemVerilog testbench language and its use in VCS. Schedule

	SystemVerilog Verification using UVM 1.1	In this course, you will learn how to build EDA industry standard UVM 1.1 testbenches. It is recommended that you take the SystemVerilog Testbench workshop before this class. Schedule

	SystemVerilog Verification using VMM 1.1	In this course, you will learn to apply the VMM 1.1 explicitly-phased Methodology using SystemVerilog language. It is recommended that you take the SystemVerilog Testbench workshop before this class. Schedule

	SystemVerilog Verification using VMM 1.2	In this course, you will learn to apply the VMM 1.2 implicitly-phased methodology using the SystemVerilog language. It is recommended that you take the SystemVerilog Testbench workshop before this class Schedule

RTL Synthesis
Design Synthesis Courses

	Design Compiler 1	This course covers the ASIC synthesis flow using Design Compiler Topographical / Graphical to generate a gate-level netlist which will result in acceptable post-placement timing and congestion. Schedule

	DFT Compiler 1	In this course you will learn to use DFT Compiler to perform RTL and gate-level DFT checks and insert scan using top-down and bottom-up flows. Schedule

Sign-Off
Design Sign-Off Courses

	PrimeTime PX	This class will show you how to use PrimeTime PX to effectively analyze Peak Power and Average Power in both UPF and non-UPF flows. Schedule

	PrimeTime 1	This course teaches you how to perform static timing analysis using PrimeTime. Quickly identify and debug your design violations by generating and interpreting timing reports. Schedule

	PrimeTime2: Debugging Constraints	This course teaches an efficient method to identify potential timing problems, identify the cause, and determine the effects of these problems. Schedule

	PrimeTime SI	The PrimeTime SI course teaches the techniques to increase the precision of your STA while taking into account crosstalk effects. Schedule

	TetraMAX 1	In this course you will learn how to use TetraMAX to perform ATPG for stuck-at faults on a post-layout chip netlist for a scan design. Schedule

	TetraMAX 2: DSM Testing	This course will teach you how to perform at-speed testing as well as the "Launch on Shift" and "Launch on System Clock" techniques to detect an at-speed fault. Schedule

Physical Implementation
Design Implementation Courses

	IC Compiler 1	This course teaches how to use IC Compiler to perform placement, power, DFT, CTS, routing, SI and optimizations to achieve design closure for a SOC. Schedule

	IC Compiler 2 Clock Tree Synthesis	This course teaches how to use IC Compiler to perform pre-CTS checks and build clock trees to achieve good quality of results (QoR). Schedule

	IC Compiler 2: Hierarchical Design Planning	This course teaches how to partition a design into hierarchical sub-blocks and creating the floorplan, constraint and timing information required for implementation. Schedule

DFM
DFM & TCAD Courses

Basic TCAD Sentaurus

This course will introduce users to basic concepts of how to use Synopsys’ TCAD tools.
Schedule

Synplicity
FPGA Implementation Courses

	Synplify Pro & Premier	The course will familiarize new students with the FPGA design flow utilizing features of the Synplify Pro product. Schedule

	Identify	This course introduces concepts on full-speed hardware debugging using the Identify toolset which provides an "embedded HDL analyzer". Schedule

	Certify	This course introduces concepts on ASIC prototyping using the Certify ASIC Prototyping tool. Schedule

	Synplify DSP	This course shows users the Synpilfy DSP design flow including model creation, implementation and architectural exploration. Schedule

Optical Design
CODE V and LightTools

CODE V and LightTools

http://www.opticalres.com/seminar/training.html

Flow and Methodology
Learn to apply a proven Synopsys methodology to your design

	Low Power Flow HLD (Front End)	In this course, using the Front-End Synopsys Eclypse Low Power Flow, you will synthesize, analyze, and verify a 65nm Multi Voltage (MV) design requiring shutdown. Schedule

	SystemVerilog Verification using VMM 1.1	In this course, you will learn to apply the VMM 1.1 explicitly-phased Methodology using SystemVerilog language. It is recommended that you take the SystemVerilog Testbench workshop before this class. Schedule

Public Classes
Instructor-led training is offered at Synopsys’ global training centers. Classes include both lecture sessions and the opportunity to practice what you learn in hands-on labs. Course Calendar

Private Classes
All standard Synopsys classes can be offered as private workshops for groups of 8 or more students. We also offer customized training designed to meet the unique needs of your design team. An expert Synopsys instructor will deliver your private class at a Synopsys training facility, at your location or via Webex®--whichever is most convenient for you. Contact us

Synopsys Virtual Classroom
The Synopsys Virtual Classroom—available as an option for private workshops—is a time- and cost- effective alternative to on-site training. The Virtual Classroom is particularly useful for geographically dispersed teams—allowing team members to efficiently train together regardless of location.

The Virtual Classroom is a web-based environment that delivers live, interactive training right to your desk, eliminating the need to travel to a traditional physical classroom. You can participate in lectures, ask the instructor questions and practice what you’ve learned with hands on labs through the EducationSphere environment--just as you would in a traditional class.

To schedule a Virtual Classroom workshop for your design team, Contact us.

On-Demand Training
Pre-recorded, self-paced training modules on a range of topics, including the latest tool features, design methodologies, and how to deal with common support issues are available on SolvNet. (a SolvNet userID is required).