Increases in the size and complexity of today’s SoC designs have intensified the challenges of low power optimization and verification.

With expertise in low power tools and techniques, Synopsys consultants can help you manage your chip’s dynamic and leakage power consumption. We will help you understand the inherent tradeoffs in using power-related technologies such as voltage islands, power and clock gating, multi-voltage design, dynamic voltage scaling, multiple threshold voltages, MTCMOS and IEEE 1801-2009 (UPF). With project requirements in mind, our consultants can then assist you in deploying the latest low-power techniques throughout the entire design flow, from synthesis, to functional verification and clock tree synthesis, through implementation and post-route optimization.

With the number and complexity of low-power design techniques escalating, verification of designs containing these techniques has become more challenging. As a low power design moves from one operating mode to another, comprehensive power-aware verification in all of the power states is required. Synopsys consultants can help you deploy new technologies that deliver the required accuracy and verification coverage for power-managed designs, including multi-voltage simulation and multi-voltage static checks.

Synopsys’ Low Power Optimization and Verification services include assistance with:

• Low power optimization and implementation
• Review scripts, power constraints and design intent, and evaluate current low-power techniques and methodologies
• Recommend and deploy new low-power methodologies including appropriate use of advanced low-power standards and techniques (IEEE 1801, DVFS, voltage islands, etc).
• Develop new scripts and integrate them for project use
• Perform power analysis and/or IR drop analysis
• Low power verification
• Develop low power test plan
• Customize low power verification test plan to guide simulation and coverage
• Verify low power constructs such as isolation, power switches, and register retention
• Verify protection cells added by synthesis, such as isolation cells, level-shifters, and retention registers
• Verify implementation of power network added during place-and-route
• Verify UPF description matches implemented design

Low Power Optimization & Verification

To get more information on how we can customize our services for you, please contact us or call your local sales representative.