Learn how DesignWare® Data Converter IP blocks can be integrated to create a flexible interface that seamlessly communicates with any RF transceiver block without penalty in the total system power dissipation
Manuel Mota, Technical Marketing Manager, Converter IP Solutions Group, Synopsys
Sep 09, 2010

In this webinar, come hear about the new IEEE specifications enabling Quality-of-Service and Energy Efficient Ethernet. You will also get an introduction to the DesignWare® Ethernet QoS and GMAC Universal MAC IP cores and how they can help you launch a new generation of networking products.
John Swanson, Senior Manager, Synopsys
Jul 29, 2010

The next generation of the PCI Express® protocol, PCI Express 3.0, incorporates significant changes that go beyond the increase in link speed from 5 GT/s to 8 GT/s. In this webinar hear about the key specification changes for the PCI Express 3.0 protocol, equalization procedure, PIPE interface and electrical interface. In addition, learn about the trade-offs and practical implementation issues through examples and lessons learned from the development of Synopsys DesignWare IP for PCI Express 3.0. Finally, get a brief overview of the DesignWare® IP for PCI Express 3.0 solution.
Frank Kavanagh, Senior Engineering Manager
May 25, 2010

In this webinar, you will get an overview of a wide range of audio functions that can be optimized for low power consumption and small silicon area such as volume control, high isolation inputs, crosstalk, headset drivers, Class-G, pop-noise suppression and clock management. You will also learn how to select the right analog audio block lineups for different types of applications, and you will understand how Synopsys’ high-quality DesignWare Audio IP solutions can deliver performance levels at par with those from discrete components
João Risques, Product Marketing Manager , Synopsys
Apr 13, 2010

This webinar details the flexible on-chip bus architecture of the DesignWare interconnect fabric that enables dedicated high-performance and shared low-performance links to be combined within a single AMBA 3 AXI on-chip interconnect, eliminating unnecessary logic within the design to deliver maximum bandwidth while reducing area, routing congestion and power.
Fred Roberts, Corporate Applications Engineer, Synopsys
Feb 10, 2010

This webinar explains how high-performance DesignWare Mixed-Signal PHY IP addresses issues such as jitter, robustness, power, testability and PVT invariance and provides insights on how to ensure high yield across process corners and manufacturing variations.
Synopsys
Oct 13, 2009

Learn about the key features in the HDMI 1.4 specification, the benefits it offers to consumers and the challenges of implementing these new features from the perspective of an SoC developer.
Manmeet Walia, Senior Product Manager for Mixed-Signal PHY IP
Sep 30, 2009

Learn about low power design requirements for long running circuits and an innovative approach to reduce the energy consumption of these circuits. Includes a brief overview of the additional power savings you can achieve using DesignWare® minPower components.
Synopsys
Sep 23, 2009

To address higher-bandwidth demand, the new USB 3.0 (aka SuperSpeed USB) standard operates at 5Gbps and delivers more than 10x the bandwidth of USB 2.0, enabling faster "sync-and-go" functionality between PCs and portable electronic devices.
Synopsys
Jul 22, 2009

In this webinar: discover the different types of I/O Virtualization, learn how I/O Virtualization is addressed within the PCI Express specification and understand the specific changes required to add I/O Virtualization to an existing PCI Express interface.
Synopsys
Jan 28, 2009

This technical webinar presents how the Synopsys DesignWare AMBA On-Chip Bus solution improves productivity during the design and verification of AMBA-based SoCs. Special emphas is placed on how DesignWare AMBA VIP leverages OpenVera™ to provide advanced verification methodologies.
Synopsys
Dec 10, 2008

This webinar discusses the impact of uncertainty effects, with emphasis on signal integrity techniques to address margin eroders such as crosstalk, simultaneously switching outputs, impedance mismatch and inter-symbol interference.
Synopsys
Oct 15, 2008

Designers and verification engineers using the AMBA 3 AXI bus protocol are faced with a unique set of challenges to both subsystem design and validation. This webinar includes a technical explanation of the xVC layer and how DesignWare VIP can be used to rerun ARM-supplied xVC-based IP validation tests.
Synopsys
Oct 13, 2008

This webinar outlines critical areas to consider for the lowest-power DDR interface, including where power is consumed in embedded DDR systems, DDR3 vs. DDR2 power, correcting the "JEDEC-ophile" DDR misconceptions, and the PCs use DIMMs/ SoCs use components (and sometimes DIMMs) conundrum.
Synopsys
Oct 01, 2008

A discussion of the common misconceptions of the DRAM market, including the realistic commodity DRAM roadmap for DDR2, DDR3 & LPDDR products. This webinar covers how the DRAM interface can affect your SoC design & package criteria.
Synopsys
Sep 16, 2008

Learn how to utilize the new DesignWare® SATA Device IP core to implement the SATA interface and see how the IP offers a flexible feature set and architecture, enabling you to achieve your performance goals while maintaining low power consumption for the overall system.
Synopsys
Jul 31, 2008

Learn to take advantage of the constrained random verification approach, and see the step-by-step methods and techniques for using DesignWare VIP with Synopsys' proven VMM Methodology Standard Library for SystemVerilog to develop a robust verification environment.
Synopsys
Jul 15, 2008

An introduction to the DesignWare Gigabit Ethernet IP solution, including multiple PHY interfaces. Learn how to include an Ethernet design in a reusable processor-independent subsystem using the DesignWare IP for AMBA in conjunction with the Ethernet IP.
Synopsys
Dec 19, 2007

DesignWare® IP for SATA AHCI Host supports the latest 2.6 SATA specification and meets the needs of existing and future designs for high-performance/low-power applications. Includes a review of power management features and optional configurations that enable ultra low power consumption.
Synopsys
Nov 07, 2007

This webinar provides an overview of the DDR2 SDRAM interface subsystem design approach Synopsys proposes and how a complete integrated solution can reduce risk and increase design quality.
Synopsys
Jul 25, 2007

This webinar demonstrates Synopsys' built-in test solution for DesignWare® PCIe®, SATA and XAUI PHY IP, where at-speed analog test can be done on a pure digital tester running at 10 MHz. Using this capability, customers have gone from first silicon to production test in under two weeks!
Synopsys
Jul 12, 2007

Are you ready to integrate high-speed USB IP into your SoCs? This discussion covers system software, protocol, and PHY integration issues common to USB implementation for ultra-low power and cost-sensitive designs.
Synopsys
Jun 27, 2007

Learn about the ARM PrimeCell infrastructure and how DesignWare VIP enables the development of a more thorough and reusable verification environment using advanced verification methodologies such as a coverage-driven constrained random verification process to quickly identify subsystem anomalies.
Synopsys
Jan 31, 2006

This webinar focuses on the challenges and solutions for high-speed serial interconnects like PCI Express, SATA and XAUI. Production testing of high-speed serial interconnects is very difficult and a solution to this problem using on-chip ATE is presented.
Synopsys
Oct 13, 2005

Designers and verification engineers using ARM's AMBA 3 AXI bus protocol protocol are faced with a unique set of verification challenges. Learn how you can address these challenges and accelerate your verification process with DesignWare VIP and the Reference Verification Methodology.
Synopsys
Aug 25, 2005

Regardless of the datapath circuit size, managing performance is very critical to meeting the overall design target. In this webinar we discuss how the best-in-class datapath technology from DC Ultra and DesignWare Library helps produce the best synthesis QoR.
Synopsys
Aug 24, 2005

First in a series of webinars that review some of the complex features of PCI Express and the economics of adding the interface to your designs. Follow-on webinars will cover PCI Express system-level design issues and achieving compliance for your products.
Synopsys
Jan 27, 2005