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Reliability and Qualification of MTP NVM IP from Commercial to Automotive Applications
How Synopsys designs and executes on a silicon testing methodology for embedded MTP NVM IP technology, enabling SoC designers with reliable and qualified solutions for their end applications
Ting-Jia Hu, Sr. Program Manager for DesignWare NVM IP, Synopsys
Jan 10, 2012 | | | Introducing the DesignWare ARC 32-bit Processor Family for Embedded Applications
Learn how the new ARC EM processor family enables development of advanced processors with optimum balance of performance, power and area; performance exceeding 1.5 DMPS/MHz; and power-efficiency of less than 2uW/DMIPS at 28-nm.
Steve Tateosian, Product Marketing Manager ARC Processors, Synopsys
Oct 25, 2011 | | | Addressing the Challenges of Designing an AMBA(R)-based SoC with a PCI Express(R) Interface
The Webinar will explore trade-offs and implementation issues through lessons learned from the development of Synopsys DesignWare IP for PCI Express solutions and the customers that have used them.
Frank Kavanagh, Senior Engineering Manager, DesignWare Digital Controllers for PCI Express, Synopsys
Oct 20, 2011 | | | Chinese Version: Build Low-power, high-performance mobile SoCs with complete MIPI solutions
Learn about the building blocks and integration challenges faced by SoC designers integrating MIPI protocols to interface to camera, display, RFIC, storage and chip to chip connectivity.
Haopeng Liu, FAE, Synopsys
Oct 17, 2011 | | | Reliability and Qualification of MTP NVM IP from Commercial to Automotive Applications
How Synopsys designs and executes on a silicon testing methodology for embedded MTP NVM IP technology, enabling SoC designers with reliable and qualified solutions for their end applications.
Martin Niset, Senior Product and Test Engineering Manager, Synopsys
Oct 05, 2011 | | | Embedded Memory Test and Repair Solution: Keeping Up with Changing Design Applications and Shrinking Process Technologies
This webinar discusses key points of interest for implementing embedded memory test, repair and diagnostics solution in today's designs.
Yervant Zorian, Chief Architect, Synopsys; Sandeep Kaushik, Product Marketing Manager, Synopsys
Sep 13, 2011 | | | Build low–power, high-performance mobile SoCs with complete MIPI solutions
Learn about the building blocks and integration challenges faced by SoC designers integrating MIPI protocols to interface to camera, display, RFIC, storage and chip to chip connectivity.
Hezi Saar, Product Marketing Manager, Synopsys
Jul 26, 2011 | | | Building High-Performance SoCs with Configurable and Extensible Processors
Learn how the configurable, extensible DesignWare® ARC™ 32-bit processors offers a broad range of features that enable you to tailor the core for your specific embedded or host application.
Mike Thompson, Sr. Product Marketing Manager, Synopsys
Apr 07, 2011 | | | HDMI: Enabling the 3D Revolution
This webinar discusses the latest trends in HDMI and how advanced features address the challenges of implementing 3D capabilities in SoC design.
Manmeet Walia, Senior Product Manager, Mixed-Signal PHY IP, Synopsys
Mar 31, 2011 | | | Implementing an Embedded Memory Subsystem in Mobile Applications
Learn how to minimize low-power design complexity for your mobile SoC applications with embedded memory IP that is optimized for power, performance and density.
Prasad Saggurti, Product Marketing Manager, Synopsys
Mar 29, 2011 | | | Using IP-XACT to Streamline SoC Design and Verification
The IEEE IP-XACT specification is a valuable format that can help solve IP integration challenges when combined with quality tools designed for an IP-based design and verification flow.
John A. Swanson, Senior Manager, Synopsys
Mar 17, 2011 | | | Considerations for Implementing an Embedded Memory Subsystem in Graphic Applications
Learn about considerations for implementing an embedded memory subsystem in graphic applications
Lisa Minwell, Product Marketing Manager, Synopsys
Feb 23, 2011 | | | Selecting the Best Non-Volatile Memory IP for RFID Applications
Get a brief overview of DesignWare NVM IP specifically multiple time programmable, one time programmable & embedded Flash/EEPROM as well as NVM specifications such as endurance and retention.
Craig Zajac, Senior Product Marketing Manager, Embedded NVM IP, Synopsys
Jan 27, 2011 | | | DDR3 PHY IP Shootout - 1600 Mbps in Wire Bond vs. Flip Chip Packaging
This webinar will compare and contrast two identical test chips using Synopsys DesignWare DDR3/2 PHY and controller IP, the first using a flip chip package and the second using a wire bond package.
Graham Allan, Senior Product Marketing Manager for Memory Interface IP, Synopsys
Jan 20, 2011 | | | Tips for Embedding Flexible Analog Interface IP into Digital SoCs for Broadband Communications
Learn how DesignWare® Data Converter IP blocks can be integrated to create a flexible interface that seamlessly communicates with any RF transceiver block without penalty in the total system power dissipation
Manuel Mota, Technical Marketing Manager, Converter IP Solutions Group, Synopsys
Sep 09, 2010 | | | The Next Generation of Ethernet: How New IEEE Standards Enable Energy Efficiency & Quality-of-Service
In this webinar, come hear about the new IEEE specifications enabling Quality-of-Service and Energy Efficient Ethernet. You will also get an introduction to the DesignWare® Ethernet QoS and GMAC Universal MAC IP cores and how they can help you launch a new generation of networking products.
John Swanson, Senior Manager, Synopsys
Jul 29, 2010 | | | Understanding PCI Express 3.0 and How to Implement the New Features
The next generation of the PCI Express® protocol, PCI Express 3.0, incorporates significant changes that go beyond the increase in link speed from 5 GT/s to 8 GT/s. In this webinar hear about the key specification changes for the PCI Express 3.0 protocol, equalization procedure, PIPE interface and electrical interface. In addition, learn about the trade-offs and practical implementation issues through examples and lessons learned from the development of Synopsys DesignWare IP for PCI Express 3.0. Finally, get a brief overview of the DesignWare® IP for PCI Express 3.0 solution.
Frank Kavanagh, Senior Engineering Manager
May 25, 2010 | | | Shaping the Perfect Audio Codec: How Your SoC Can Benefit from the Right Audio Functions’ Line-Ups
In this webinar, you will get an overview of a wide range of audio functions that can be optimized for low power consumption and small silicon area such as volume control, high isolation inputs, crosstalk, headset drivers, Class-G, pop-noise suppression and clock management. You will also learn how to select the right analog audio block lineups for different types of applications, and you will understand how Synopsys’ high-quality DesignWare Audio IP solutions can deliver performance levels at par with those from discrete components
João Risques, Product Marketing Manager , Synopsys
Apr 13, 2010 | | | DesignWare IP for AMBA 3 AXI On-Chip Bus
This webinar details the flexible on-chip bus architecture of the DesignWare interconnect fabric that enables dedicated high-performance and shared low-performance links to be combined within a single AMBA 3 AXI on-chip interconnect, eliminating unnecessary logic within the design to deliver maximum bandwidth while reducing area, routing congestion and power.
Fred Roberts, Corporate Applications Engineer, Synopsys
Feb 10, 2010 | | | Guidelines for Mixed-Signal PHY IP Integration, Debug and Test
This webinar explains how high-performance DesignWare Mixed-Signal PHY IP addresses issues such as jitter, robustness, power, testability and PVT invariance and provides insights on how to ensure high yield across process corners and manufacturing variations.
Synopsys
Oct 13, 2009 | | |
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