Ambassador Hotel
Hsinchu, TaiwanWednesday, August 18, 2010
Thursday, August 19, 2010
Wednesday, August 18, 2010| Time | Description | | 8:00-9:15 | Registration and Breakfast | | 9:15-10:25 | Welcome and Synopsys Keynote
Chi-Foon Chan, President & Chief Operating Officer, Synopsys | | 10:25-10:45 | Break | | 10:45-11:00 | SNUG Technical Committee Presentation
Dr. Shih-Arn Huang, Deputy Director of RD Center, Realtek
Chairman of SNUG Techncial Committee | | 11:00-12:00 | Vision Speech - The Evolution of Synthesis
Don Chan, Vice President, Synopsys | | 12:00-13:30 | Lunch | | | | Physical Implementation | Low Power Solution | AMS Verification | FPGA/IP | | 13:30-15:30 | WA1 - ICC
N40 DFM Implementation Flow
TSMC Reference Flow
TSMC IC Compiler Planning and Implementation of Large Hierarchical Designs
Synopsys
| WA2 - UPF Solutions
Experience Sharing on IC Compiler Adoption
Etron Low Power Design & Verification for PACDSP
ITRI Low Power Verification Methodology for a hierarchical design with handicapped UPF
TSMC Low Power Verification
Synopsys
| WA3 - Fast SPICE
How to verify design reliability issue with HSIM
TSMC Flash Memory IR/EM analysis using HSIMPlus
MXIC
CustomSim-CircuitCheck (CCK)
Synopsys | WA4 - FPGA Solutions
SNPS USB 3.0 Prototyping Experience Sharing on HAPS52
Realtek Prototyping Performance Comparison on MIMO Project Using HAPS34 and HAPS54ITRI Advanced RTL debug Solution for Peripheral Device Interface
Nuvoton Experience Sharing of Successful debugging cases in FPGA system verification
Faraday | | 15:30-16:00 | Break | | 16:00-18:00 | WB1 - ICC/Lynx
Easy to access UMC technology by Lynx FRS Design System
UMC A Case Study: In-Design Rail and In-Design Timing by using ICC
ALI In-Design Signoff-Quality DRC & Fill using IC Validator within IC Compiler
UMC Core-Package-PCB co-simulation with Reduced-Core-Model
Himax | WB2 - UPF Solutions
MVRC/MVSIM enables TSMC N28/N40 Product Qualification Vehicle (PQV) chip design
TSMC Low Power Multi-Voltage Design Implementation Methodology using the IEEE 1801 (UPF) StandardSynopsys
| WB3 - Fast SPICE/Co-sim/Extraction
Analog Reference Flow
TSMC SOC & IP System Verification Methodology with Nanosim-VCS Cosim
Novatek Power Characterization With NanoTime
TSMC AMS Verification Solutions
Synopsys | WB4 - FPGA/IP
System Validation using IP-XACT standards
ARM Performance Matched Design for Multi-level Memory Hierarchy in a Multi-core SoC
Andes
The latest protocols and cooperation with Synopsys DesignWare IP solutionSynopsys HAPS-60 -- The Next-generation Rapid Prototyping Platform Introduction
Synopsys |
|
Thursday, August 19, 2010| Time | Description | | 8:00-9:10 | Registration and Breakfast | | 9:10-10:00 | Synopsys Speech
Evolution of Design Methodology
Don Chan, Vice President, Synopsys | | 10:00-10:30 | Partner Speech
Cliff Hou, Senior Director, TSMC | | 10:30-10:50 | Break | | 10:50-11:30 | Synopsys Vision Speech
Verification Challenges for the Next Decade
Janick Bergeron, Fellow, Synopsys | | 11:30-12:00 | Partner Speech
Philip Lu, President, ARM Taiwan | | 12:00-13:30 | |  | Physical Implementation | Synthesis/STA/Test | Function Verification/ESL | | 13:30-15:30 | TA1 - ICC/Lynx
Low power CTS technique using optimal ICG placement
Mediatek Multi-Media design put into use ICC ILM flow
Realtek Predictable Schedule and Instant Access to Advanced Technology with Lynx Design System
Synopsys | TA2 - Primetime/Test/3D
Boost PrimeTime Productivity Using Multicore
VIA Scan Test Power Reduction Using Power-aware ATPG
Realtek 3D IC Implementation
ITRI Reduce Power Consumption in High Performance IP with Synopsys Designware minPower Solution
Faraday | TA3 - VMM
Adopting vmm_subenv in SOC projects
Realtek Methodology of Executable Verification Plan
Sunplus VMM 1.2 Tutorial
Synopsys
| | 15:30-16:00 | Break | | 16:00-17:00 | TB1 - ICC
Streamline text shorts detection with IC Validator
Synopsys IC Compiler Feasibility Flow
Synopsys | TB2 - RTL Synthesis
Galaxy RTL: Design Compiler Family 2010.03 Update | TB3 - VMM/ESL
Using VMM to Address DTV Transport Processor Verification Challenges
Realek ESL Virtual Platform for System Performance Enhancement
ITRI | | 17:00-17:30 | Best Paper Award & Lucky Draw | | 17:30-19:00 | SNUG Taiwan 10th Anniversary - Engineer Night |
|