The development of increasingly complex embedded systems requires a design methodology that supports abstract modeling focused on system behavior, underpinned by tools that enable architectural exploration, verification and implementation of these complex systems. The System-Level Catalyst program enables the integration of Axilica's behavioral synthesis from UML behavioral models of hardware with the advanced capabilities for platform verification offered within the Synopsys Virtualizer Platform. - Suresh Radia, CEO, Axilica Limited

Product Description
Axilica's product, FalconML, provides behavioral synthesis from system level models described in UML (Unified Modeling Language) to an RTL hardware description (VHDL, Verilog) for implementation in an FPGA or ASIC, or a SystemC TLM description for high-performance functional simulations.

FalconML's support for the modeling standards UML and SysML, used in the modeling of systems and software, extends the use of UML for the modeling and implementation of hardware in complex embedded systems. FalconML reads the UML models captured in a number of existing commercial UML modeling tools and synthesizes the design according to a defined number of user options.

• RTL (Hardware) option: FalconML produces RTL in either VHDL and Verilog which can be used as a direct input for an RTL synthesis tool targeting, for example, FPGA or ASIC implementation. FalconML introduces clock and reset signals needed for hardware implementation, includes both UML and hardware state machines, memory elements (registers, RAM, ROM) and unrolls loops.
• Hardware-software co-design: parts of the UML models can be identified for implementation in either hardware or software. Hardware implementation generates VHDL or Verilog (RTL option). Software is generated in C++ for compilation on a POSIX conformant embedded OS or a multi-tasking RTOS such as FreeRTOS/OpenRTOS
• SystemC: FalconML supports TLM-2.0 for fast system simulation
• C++: FalconML can generate a complete C++ description of the models captured in UML enabling full system simulation in a standard C++ IDE.

Interoperability Description and Customer Benefit:
FalconML links system level modeling methods used in model driven UML tools with the existing hardware design flows provided by Synopsys. FalconML enables Synopsys' customers developing complex embedded systems and complex hardware components, such as FPGA's within an embedded system, to model system behavior in UML and use FalconML to generate the corresponding SystemC TLM or RTL description. The SystemC description can be used for advanced platform development within the Synopsys Virtualizer environment. The RTL description can be synthesized using Synopsys' leading edge products (Synplify PRO and Design Compiler). The RTL can be verified via simulation in VCS.

FalconML enables the use of UML modeling as a front-end to the Synopsys hardware design environment delivering a higher-level model-based design methodology that provides rapid hardware prototyping, system level verification with SystemC, and hardware/software co-design capabilities that results in better quality designs, lower development costs and faster time to market.