This list outlines all of the standards and committees that Synopsys is involved in.
A:Accellera - Interface Technical CommitteeAccellera - OVL (Open Verification Library)Accellera - UCIS (Unified Coverage Interoperability Standard)Accellera - Verification IP Technical SubcommitteeAccellera - Verilog AMSASI-SIG - Compliance Working Group
D:DDR PHY Interface (DFI)DEF - Design Exchange Format
F: FSA - Hard IP Quality Risk Assessment Tool
G: GDSII
I:IEEE P1735 - IP Encryption - formerly with VSIAIEEE 1149.1 - Boundary ScanIEEE 1149.4 - Mixed-Signal Test BusIEEE 1149.7 - Boundary Scan ArchitectureIEEE 1364 - VerilogIEEE 1364.1 - RTL Synthesis VerilogIEEE 1450 - STILIEEE 1450.6.1 - OCI (Open Compression Interface) IEEE 1497 - SDF (Standard Delay Format)IEEE 1666 - SystemCIEEE 1800 - SystemVerilogIEEE 1850 - PSLIEEE P1734 - IP Quality (QIP) formerly with VSIAIEEE 1801 - Low Power Format (based on Accellera UPF)IP-XACT - Verification WGISO 23360:2006 Linux Standard Base
L:LEF - Library Exchange Format
M: MIPI
O: OASIS® (Open Artwork System Interchange Standard)OSCI
P: PCI-SIG Power.org
S: SOI ConsortiumSPIRIT ConsortiumSynopsys - ITF (Interconnect Technology Format)Synopsys - LibertySynopsys - MilkywaySynopsys - Open VeraSynopsys - OpenMASTSynopsys - SAIF (Switching Activity Interchange Format)Synopsys - SDC (Synopsys Design Constraints)
U: USB-IF
V: VHDL
W:WiMedia