This list outlines all of the standards and committees that Synopsys is involved in.

A:
Accellera - Interface Technical Committee
Accellera - OVL (Open Verification Library)
Accellera - UCIS (Unified Coverage Interoperability Standard)
Accellera - Verification IP Technical Subcommittee
Accellera - Verilog AMS
ASI-SIG - Compliance Working Group

D:
DDR PHY Interface (DFI)
DEF - Design Exchange Format

F:
FSA - Hard IP Quality Risk Assessment Tool

G:
GDSII

I:
IEEE P1735 - IP Encryption - formerly with VSIA
IEEE 1149.1 - Boundary Scan
IEEE 1149.4 - Mixed-Signal Test Bus
IEEE 1149.7 - Boundary Scan Architecture
IEEE 1364 - Verilog
IEEE 1364.1 - RTL Synthesis Verilog
IEEE 1450 - STIL
IEEE 1450.6.1 - OCI (Open Compression Interface)
IEEE 1497 - SDF (Standard Delay Format)
IEEE 1666 - SystemC
IEEE 1800 - SystemVerilog
IEEE 1850 - PSL
IEEE P1734 - IP Quality (QIP) formerly with VSIA
IEEE 1801 - Low Power Format (based on Accellera UPF)
IP-XACT - Verification WG
ISO 23360:2006 Linux Standard Base

L:
LEF - Library Exchange Format

M:
MIPI

O:
OASIS® (Open Artwork System Interchange Standard)
OSCI

P:
PCI-SIG
Power.org

S:
SOI Consortium
SPIRIT Consortium
Synopsys - ITF (Interconnect Technology Format)
Synopsys - Liberty
Synopsys - Milkyway
Synopsys - Open Vera
Synopsys - OpenMAST
Synopsys - SAIF (Switching Activity Interchange Format)
Synopsys - SDC (Synopsys Design Constraints)

U:
USB-IF

V:
VHDL

W:
WiMedia